ASIC Design Engineers
ASIC Design, Bucks, £27-36k
A manufacturer of electronic equipment seeks an ASIC design engineer with 3 - 4 years experience of VHDL, Verilog and Cadence.
ASIC Design Engineer, Essex, £18-35k
A major telecommunications company are looking for additional engineers to join a successful team developing innovative ATM technology. Applicants should have some of the following :- ASIC System Design and Specification, digital design using VHDL or Verilog, Synopsis, ATM or JTAG.
Digital ASIC Design, Surrey, £23-33k
An Engineer with 1+ years experience is sought for the specification and design of ASIC signal processing structures. Applicants should have a good knowledge of digital logic design together with some of :- VHDL, VLSI, Synthesis, Synopsis, Mentor, FPGAs or Verilog.
ASIC Design Engineers, Bucks, 25-35k
If you and an engineer with at least two years ASIC design experience using VHDL or Verilog and Synthesis then our client will be interested in you.
ASIC Product Engineer, Surrey, £23-28k
Our client is looking for a hands in engineer who is able to system test ASIC engineering samples in a lab environment. Good hardware skills are needed as well as experience in debugging PCBs. Experience or interest in 3D graphics would be an advantage.
Analogue / Digital IC Designers, Wilts, £25-30k
Our client has several positions for engineers with experience of developing digital ASICs or analogue ICs.
RF IC Designer, Surrey, £24-36k
A designer of mobile communications systems is looking to recruit a design engineer with 3 years experience of IC design, including : designing BiCMOS RF ICs up to 3 GHz, Low noise low power design techniques, amplifiers / mixers / LNA / Buffers. some knowledge of the following is desirable, but not essential :- VHF/UHF PLL / DDS synthesisers or CMOS / Bipolar / GaAs / PA & system design up to 2GHz.
ASIC Applications Engineer, Bucks, £25-35k
Our client is looking for engineers with a strong ASIC background and a good understanding of present design flows, tools and methodologies.
ASIC Designers, Surrey, £20-30k
A designer of 3D graphics products is looking for engineers with 2 years ASIC development experience using VHDL or Verilog. Some knowledge of C/C++ and Synopsis would be beneficial, as would 3D graphics knowledge.
ASIC Designers, Hants, £20-35K
CMOS IC design engineers with 2 years or more experience in full custom
ASIC design and good VHDL skill are wanted by our clients.
Synopsys and analogue/mixed signal CMOS are an advantage.
ASIC Designers, Essex, £26-30k
ASIC engineers with several years experience of high speed complex
digital ASIC designs using VHDL are sought by our clients. Knowledge
of Cadence, Synopsys or VLSI layout would be beneficial.
ASIC / Analogue & Mixed Signal Designers, Berks, £23-37K
Our client is looking for Engineers with three to five years experience
of either ASIC HDL design (using either VHDL or Verilog) or bipolar / BiCMOS
/ CMOS designs.
ASIC Designers, Hants, £20-35K
CMOS IC design engineers with 2 years or more experience in full custom
ASIC design and good VHDL skill are wanted by our clients.
Synopsys and analogue/mixed signal CMOS are an advantage.
VLSI ASIC Design Engineers, Wilts, to £35k
The successful candidate will be responsible for
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Development of detailed ASIC specifications based on general or specific
applications requirements.
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Development of appropriate higher level circuit models including 'C' and
VHDL/Verilog behavioural descriptions.
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Design and layout digital VLSI circuit blocks up to complete embedded core
ASIC to meet circuit specifications and defined quality standards.
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Define and generate appropriate characterisation and production test specifications,
including minimum access requirements.
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Provide complete design documentation including data sheets.
The designer will work as part of a team, often on specific projects, in
additions to general development support. Applicants should be degree qualified,
preferable 1st class or 2.i, in an Electronics or related subject, and
have at least 3 years experience in VLSI design,.
Senior Design Engineer, Hants, to £32k
Involved in sub-micron CMOS design, covering memory and logic circuits,
you will have around 6 years experience of transistor level design from
Spice through to layout. You will be responsible for a small engineering
team to ensure that the completed designs meet their planned targets.
Consumer Product Design (Digital Video), Berks
Working as a part of a team developing digital video ICs, you will have
a background including ASIC design using HDL simulation and synthesis,
and a knowledge of digital video or digital compresion would be useful.
Digital ASIC Designers, Manufacturers of Mobile Phones, Surrey
A vacancy in a small, innovative team using state of the art tools and
design techniques to develop ASICs for future generations of mobile phones.
The position will involve ASIC design from specification through to silicon.
Candidates should ideally have :-
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Good first degree (1st or 2.i)
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2 years + experience of digital ASIC design
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VHDL literacy
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Experience of complete ASIC design process
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Synthesis experience (preferably Synopsys)
ASIC Designer, Wilts
A position exists for an ASIC designer to join a team of highly skilled
and motivated engineers designing ASICS for GSM cellular basestations.
The key responsibilities will be :-
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Requirement capture
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Top Down Design methodology
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VHDL
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Synthesis
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Simulation
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Design for test
You will be educated to degree level, with a 2.ii or better, have between
2 to 5 years experience in delivering ASICs, and understanding of ASIC
design for large systems. A working knowledge of Mentor graphics V8 design
tools would be an advantage.
Design Engineer, Hants, to £25k
Design engineers with 2 to 5 years experience and educated to degree level
are needed to join a world class manufacturer of high performance semiconductors.
You would have gained experience in all aspects of advanced CMOS technology,
preferably including experience of memory design. You will be highly motivated
and capable of working on your own initiative.
Senior Design Engineer, Cheshire, £Excellent
A vacancy for a senior design engineer offering experience experience of
full custom digital CMOS design,verification, layout, SPICE, and logic
simulation. As well as these low level skills, the position will require
some systems-level expertise. Experience with the design and implementation
of mixed-signal systems would be advantageous.
The successful candidates will work as part of a small team developing
novel field-programmable structures, and can expect to contribute to all
aspects of device specification and development. You should be self motivated,
creative and team spirited with at least years relevant experience. Requirements
are :-
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Cadence design capture layout and verification
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SPICE and logic simulation
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Transistor and gate level circuit design
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The ability to organise and motivate oneself
3 Branksome Way, New Malden, Surrey, KT3 3AX
Tel : 0181 - 549 0100 or Fax: 0181 - 549 9771
email : consult@applerec.u-net.com